D/a converter circuit and its voltage supply control method

ABSTRACT

A DAC includes a DAC unit that selects one of a plurality of selection voltages according to an input digital signal, and outputs the selected selection voltage as an analog signal, a first power-supply voltage terminal through which a first power-supply voltage is supplied to a first terminal of a transistor constituting the DAC unit upon power-up of the DAC unit, and a voltage supply control unit that detects a potential difference between the first power-supply voltage and a second voltage used to generate the selection voltages, outputs a voltage corresponding to the first power-supply voltage to a second terminal of the transistor constituting the DAC unit when the potential difference is larger than a predetermined value, and outputs a voltage corresponding to the second voltage to the second terminal of the transistor constituting the DAC unit when the potential difference is smaller than the predetermined value.

INCORPORATION BY REFERENCE

This application is based upon and claims the benefit of priority fromJapanese patent application No. 2009-290360, filed on Dec. 22, 2009, thedisclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Field of the Invention

The present invention relates to a D/A converter circuit and its voltagesupply control method.

2. Description of Related Art

In recent years, the development of large flat display devices hasbecome increasingly active. Among these large flat displays, LCDs(Liquid-crystal Displays) are getting attention because of their lowerpower consumption and other merits. LCDs are equipped with an LCD driverIC (Integrated Circuit) that drives pixels arranged in matrix on thedisplay.

FIG. 12 shows a configuration of an LCD driver IC1 in related art. Asshown in FIG. 12, the LCD driver IC1 includes a logic circuit 10, alevel-shifter 20, a D/A converter (DAC) circuit 30, and an output-stagebuffer 40.

The logic circuit 10 generates digital gray-scale signals each of whichis composed of n bits (hereinafter, an assumption is made that n=6) andwhich are used to determine the gray-scale signal of each pixel. Notethat the digital gray-scale signal has a CMOS signal level, e.g., avoltage around 4V.

The level-shifter 20 shifts the level of a digital gray-scale signalgenerated by the logic circuit 10 to a high potential around 10V.

The DAC circuit 30 converts a digital gray-scale signal output from thelevel-shifter 20 into an analog gray-scale signal. The DAC circuit 30selects one of supplied selection voltages VP1 to VP64 and one ofselection voltages VN1 to VN64 and outputs the selected voltages to theoutput-stage buffer 40 in order to generate the analog gray-scalesignal.

The output-stage buffer 40 performs current-buffering for the analoggray-scale signal supplied from the DAC circuit 30, and outputs thebuffered current to display pixels.

FIG. 13 shows the configuration of the DAC circuit 30. As shown in FIG.13, the DAC circuit 30 includes a PchDAC 31, an NchDAC 32, and a ladderresistor unit 33. Note that in LSDs, it is necessary to reverse thepolarity of voltage applied between a pixel electrode and its opposedelectrode at certain intervals in order to prevent the degradation ofthe liquid-crystal material. Polarity switches SW51 and SW52, which areprovided to perform this polarity reverse of voltage applied to thepixel electrode, are connected on the input side and the output side,respectively, of the DAC circuit 30.

The ladder resistor unit 33 receives voltages VP1, VP64, VN1 and VN64from external terminals TVP1, TVP64, TVN1 and TVN64 respectively, andgenerates selection voltages VP1 to VP64 and selection voltages VN1 toVN64 (which are described later). Note that there are relations“VP1>VP64” and “VN1<VN64”.

The PchDAC 31 receives a digital gray-scale signal from thelevel-shifter 20, selects one of the selection voltages VP1 to VP64according to the digital gray-scale signal, and outputs the selectedselection voltage as an output selection voltage VPout. The NchDAC 32receives a digital gray-scale signal from the level-shifter 20, selectsone of the selection voltages VN1 to VN64 according to the digitalgray-scale signal, and outputs the selected selection voltage as anoutput selection voltage VNout.

FIG. 14 shows a graph showing a relation between input digitalgray-scale signals and output analog gray-scale signals of the DACcircuit 30. Note that FIG. 14 shows a relation in an example where thepanel is normally-while and the input digital signal has six bits. Asshown in FIG. 14, when a digital gray-scale signal D[5:0] is [000000] inthe positive-polarity output state, for example, the PchDAC 31 selectsand outputs the selection voltage VP1. Further, when the digitalgray-scale signal D[5:0] is [000001], the PchDAC 31 selects and outputsthe selection voltage VP2. The PchDAC 31 operates in a similar fashionfor the subsequent digital gray-scale signals. Finally, when the digitalgray-scale signal D[5:0] is [111111], the PchDAC 31 selects and outputsthe selection voltage VP64. In the negative-polarity output state,similar digital-analog conversions are performed with the NchDAC 32.

FIG. 15 shows a detailed configuration of the PchDAC 31 and the ladderresistor unit 33. Note that as for the ladder resistor unit 33, only thepart of configuration corresponding to the PchDAC 31 is illustrated.

As shown in FIG. 15, the ladder resistor unit 33 includes resistiveelements R1 to R63. The ladder resistor unit 33 generates intermediatevoltages VP2 to VP63 between the voltages VP1 and VP64, which areapplied from the external terminals TVP1 and TVP64 respectively, atrespective nodes each between one of the resistive elements R1 to R63and its neighboring resistive element. Further, the ladder resistor unit33 outputs these voltages as selection voltage VP1 to VP64 to the PchDAC31.

The PchDAC 31 includes switch circuits SW1_1 to SW1_32 SW2_1 to SW2_16,SW3_1 to SW3_8, SW4_1 to SW4_4, SW5_1, SW5_2, and SW6_1. For example,the switch circuit SW1_1 receives the selection voltages VP1 and VP2 andoutputs one of the received selection voltages VP1 and VP2 according tothe value of the LSB (Least Significant Bit), i.e., D[0] of a 6-bitdigital gray-scale signal. Similarly, each of the switch circuits SW1_2to SW1_32 receives its corresponding two selection voltages among theselection voltages VP3 to VP64, and outputs one of the receivedselection voltages according to the value of the digital gray-scalesignal D[0].

Next, for example, the switch circuit SW2_1 receives the output voltagesof the switch circuits SW1_1 and SW1_2 and outputs one of the receivedvoltages according to the value of the digital gray-scale signal D[1].Similarly, each of the switch circuits SW2_2 to SW2_16 receives itscorresponding two output voltages among the output voltages of theswitch circuits SW1_3 to SW1_32, and outputs one of the receivedvoltages according to the value of the digital gray-scale signal D[1].

Next, for example, the switch circuit SW3_1 receives the output voltagesof the switch circuits SW2_1 and SW2_2 and outputs one of the receivedvoltages according to the value of the digital gray-scale signal D[2].Similarly, each of the switch circuits SW3_2 to SW3_8 receives itscorresponding two output voltages among the output voltages of theswitch circuits SW2_3 to SW2_16, and outputs one of the receivedvoltages according to the value of the digital gray-scale signal D[2].

Next, for example, the switch circuit SW4_1 receives the output voltagesof the switch circuits SW3_1 and SW3_2 and outputs one of the receivedvoltages according to the value of the digital gray-scale signal D[3].Similarly, each of the switch circuits SW4_2 to SW4_4 receives itscorresponding two output voltages among the output voltages of theswitch circuits SW3_3 to SW3_8, and outputs one of the received voltagesaccording to the value of the digital gray-scale signal D[3].

Next, for example, the switch circuit SW5_1 receives the output voltagesof the switch circuits SW4_1 and SW4_2 and outputs one of the receivedvoltages according to the value of the digital gray-scale signal D[4].Similarly, the switch circuit SW5_2 receives the output voltages of theswitch circuits SW4_3 and SW3_4, and outputs one of the receivedvoltages according to the value of the digital gray-scale signal D[4].

Finally, the switch circuit SW6_1 receives the output voltages of theswitch circuits SW5_1 and SW5_2 and outputs one of the received voltagesas an output selection voltage VPout according to the value of the MSB(Most Significant Bit), i.e., D[5] of the 6-bit digital gray-scalesignal.

FIG. 16 shows the configuration of the switch circuit SW1_1. Each of theother switch circuits SW1_2 to SW1_32, SW2_1 to SW2_16, SW3_1 to SW3_8,SW4_1 to SW4_4. SW5_1, SW5_2 and SW6_1 has a similar configuration tothat of the switch circuit SW1_1, and therefore their explanations areomitted. As shown in FIG. 16, the switch circuit SW1_1 includes PMOStransistors MPH and MPL, and an inverter circuit IVL. Note that, for thesake of convenience, the example shown in FIG. 16 is drawn as if everyswitch circuit includes an inverter. However, in practice, it is commonto generate a signal D[5:0] and its inverted signal outside the DAC andsupply the generated signals to respective switches. Such configurationsmay be also employed.

The selection voltage VP1 is input to either one of the source and thedrain of the PMOS transistor MPH, and the other one of the source andthe drain is connected to a node A. Further, the digital gray-scalesignal D[0] is input to the gate of the PMOS transistor MPH.

The selection voltage VP2 is input to either one of the source and thedrain of the PMOS transistor MPL, and the other one of the source andthe drain is connected to the node A. Further, the inverted signal/D[0]of the digital gray-scale signal D[0], which is obtained through theinverter IVL, is input to the gate of the PMOS transistor MPL.

The back-gates of the PMOS transistors MPH and MPL are both connected toa power-supply voltage terminal VDD2.

Note that the NchDAC 32 has a fundamentally similar configuration tothat of the PchDAC 31 except for the voltage of the back-gate. Further,the part of the ladder resistor unit 33 corresponding to the NchDAC 32also has a fundamentally similar configuration to that of the PchDAC 31.

FIG. 17 shows a schematic diagram showing a sequence of the LCD driverIC1 performed upon power-up. Note that the voltage supplied to the LCDdriver IC1 shown in FIG. 12 includes a power-supply voltage VDD1 around4V that is used by the logic circuit 10 capable of operating at a lowvoltage, and a power-supply voltage VDD2 for high-voltage driver powersupply of 10V or higher that is actually used to drive the pixels of theliquid-crystal panel. Further, it also includes the above-describedexternal voltages that are used to supply desired voltages to the DACcircuit 30. In the example shown in FIG. 13, the voltages VP1, VP64, VN1and VN64 correspond to the external voltages.

As shown in FIG. 17, firstly, the power-supply voltage VDD1 around 4Vfor use in the logic circuit 10 rises at a time t1. Then, at a time t2,the logic circuit 10 starts to operate and thereby outputs an outputsignal SGNL. Further, at a time t3, the power-supply voltage VDD2 forhigh-voltage driver power supply rises. Then, the voltages VP1, VP64,VN1 and VN64, which are voltages supplied from the external terminals,rise at a time t4.

As described above, in the DAC circuit 30 of the LCD driver IC1 (inparticular, R-DAC scheme), externally-supplied power-supply voltagesVDD1 and VDD2, voltages obtained by dividing externally-suppliedexternal voltages inside the IC, or voltages obtained by a similarmanner are exerted on each component of the DAC circuit 30.

Note that in the case of source drivers IC for dot inversion drive,there are positive-polarity output and negative-polarity output. Whenthe above-described LCD driver IC1 is used as a source driver for dotinversion drive, each of the positive-polarity side DAC circuit (PchDAC31 of FIG. 13) and the negative-polarity side DAC circuit (NchDAC 32 ofFIG. 13) only needs to have a withstand voltage equivalent to the halfof the power-supply voltage VDD2 as explained above with reference toFIG. 14. That is, the withstand voltage between the back-gate and thesource, between the back-gate and the drain, and between the back-gateand the gate of the PMOS transistor constituting each switch circuit ofthe PchDAC 31 only needs to be about the half of the power-supplyvoltage VDD2. Such a low-withstand-voltage transistor requires a smalltransistor area. Therefore, it is possible to achieve chip-shrinkingcorresponding to the withstand voltage equivalent to the half of thepower-supply voltage VDD2 in the DAC circuit 30.

Note that Japanese Unexamined Patent Application Publication No.8-179270 (Patent document 1) discloses a technique to preventmalfunctions from occurring upon power-up in source drivers and thelike. Further, Japanese Unexamined Patent Application Publication No.8-264792 (Patent document 2) discloses a technique to preventdestruction of components that would otherwise occur at the time ofpower-on of the power supply for liquid-crystal drive when the power-onis performed in an incorrect sequence.

SUMMARY

The present inventors have found the following problem. As describedabove, the chip-shrinking corresponding to the withstand voltageequivalent to the half of the power-supply voltage VDD2 is possible inthe LCD driver IC1 for dot inversion drive. However, as shown in FIG.17, for example, since the voltages VP1 and VP64 supplied from theexternal terminals have not risen sufficiently at a time t5, thepotential difference VR from the power-supply voltage VDD2 could exceedthe half of the power-supply voltage VDD2. In such a situation, thepotential difference exceeds the withstand voltage between the back-gateand the source, between the back-gate and the drain, and between theback-gate and the gate of the PMOS transistor constituting each switchcircuit of the positive-polarity side DAC circuit (PchDAC 31 of FIG.13). As described above, there is a possibility that a voltage higherthan the withstand voltage is transiently exerted on the components ofthe positive-polarity side DAC circuit (PchDAC 31 of FIG. 13) uponpower-up. Therefore, the margin of the component-withstand-voltagecannot be reduced, thus imposing a restriction on the chip-shrinking.

Further, as a countermeasure to avoid such a state that a voltage higherthan the withstand voltage is transiently exerted on the component ofthe positive-polarity side DAC circuit as described above, it isnecessary to add an additional control circuit that controls thepower-up sequence in the power supply that generates the voltages VP1and VP64 supplied through the external terminals. However, thiscountermeasure requires adding the additional control circuit in thepower supply that supplies the voltages through the external terminals,thus causing demerits such as increase in the design costs and increasein the circuit size. As a result, the merit obtained by carrying out thechip-shrinking could be cancelled out.

Further, Patent document 1 also discloses a method for bringing inputsignals to the gray-scale voltage circuit itself into a high-impedancestate for a certain period after the power-on. However, in this circuitdisclosed in Patent document 1, it is necessary to add transistorsconstituting switches used to bring the input signals into ahigh-impedance state as well as its control circuit having a withstandvoltage equivalent to VDD2. Therefore, the layout size of the chipcannot be reduced.

Meanwhile, Patent document 2 discloses a semiconductor device (driver)including therein switch elements that operate so that power-supplyvoltages are supplied into the semiconductor device in order inaccordance with a certain sequence, and a circuit that controls thatsequence operation. However, this circuit also requires usingtransistors capable of withstanding VDD2 not only for the additionaltransistors constituting switches and the like that produce thepower-supply sequence inside the circuit, but also for other componentsin the circuit. Therefore, the layout size of the chip cannot bereduced.

A first exemplary aspect of the present invention is a D/A convertercircuit for a drive circuit provided in a display device, including: aD/A converter unit that selects one of a plurality of selection voltagesaccording to an input digital gray-scale signal, and outputs theselected selection voltage as an analog gray-scale signal; a firstpower-supply voltage terminal through which a first power-supply voltageis supplied to a first terminal of a transistor constituting the D/Aconverter unit upon power-up of the D/A converter unit; and a voltagesupply control unit that detects a potential difference between thefirst power-supply voltage and a second voltage used to generate theselection voltages, outputs a voltage corresponding to the firstpower-supply voltage to a second terminal of the transistor constitutingthe D/A converter unit when the potential difference is larger than apredetermined value, and outputs a voltage corresponding to the secondvoltage to the second terminal of the transistor constituting the D/Aconverter unit when the potential difference is smaller than thepredetermined value.

In the D/A converter circuit in accordance with an exemplary aspect ofthe present invention, the voltage between the first and secondterminals of the transistor constituting the D/A converter unit neverincreases to or above the predetermined value. Therefore, it is possibleto set the withstand voltage between the first and second terminals ofthe transistor constituting the D/A converter unit to a value equal toor smaller than the predetermined value.

The D/A converter in accordance with an exemplary aspect of the presentinvention can control the withstand voltage of transistor componentsconstituting the circuit to a value equal to or smaller than thepredetermined value, thus making it possible to reduce the componentsize and thereby to achieve the chip-shrinking.

BRIEF DESCRIPTION OF THE DRAWING

The above and other exemplary aspects, advantages and features will bemore apparent from the following description of certain exemplaryembodiments taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is an example of a configuration of a DAC circuit in accordancewith a first exemplary embodiment of the present invention;

FIG. 2 is an example of a voltage supply control circuit in accordancewith a first exemplary embodiment of the present invention;

FIG. 3 is a timing chart for explaining an operation of a voltage supplycontrol circuit in accordance with a first exemplary embodiment of thepresent invention;

FIG. 4 shows a detailed configuration of a PchDAC and a ladder resistorunit in accordance with a first exemplary embodiment of the presentinvention;

FIG. 5 is a schematic diagram showing a sequence of an LCD driver IC inaccordance with a first exemplary embodiment of the present inventionperformed upon power-up;

FIG. 6 is another example of a voltage supply control circuit inaccordance with a first exemplary embodiment of the present invention;

FIG. 7 is an example of a voltage supply control circuit in accordancewith a second exemplary embodiment of the present invention;

FIG. 8 is a timing chart for explaining an operation of a voltage supplycontrol circuit in accordance with a second exemplary embodiment of thepresent invention;

FIG. 9 is a schematic diagram showing a sequence of an LCD driver IC inaccordance with a second exemplary embodiment of the present inventionperformed upon power-up;

FIG. 10 is another example of a voltage supply control circuit inaccordance with a second exemplary embodiment of the present invention;

FIG. 11 shows a detailed configuration of a PchDAC and a ladder resistorunit in accordance with another exemplary embodiment of the presentinvention;

FIG. 12 is a block diagram of a typical LCD driver IC;

FIG. 13 is an example of a configuration of a DAC circuit in relatedart;

FIG. 14 is a graph showing a relation between an input digitalgray-scale signal and an output analog gray-scale signal of a typicalDAC circuit;

FIG. 15 shows a configuration of a typical PchDAC;

FIG. 16 shows a configuration of a switch circuit provided in a typicalPchDAC; and

FIG. 17 is a schematic diagram showing a sequence of an LCD driver IC inrelated art performed upon power-up.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS First ExemplaryEmbodiment

A first specific exemplary embodiment to which the present invention isapplied is explained hereinafter in detail with reference to thedrawings. In this first exemplary embodiment, the present invention isapplied to a DAC circuit 100 of an LCD driver 1C of a liquid-crystaldisplay device. Note that the configuration of the LCD driver ICincluding the DAC circuit in accordance with this first exemplaryembodiment is similar to that of the LCD driver IC1 shown in FIG. 12except that the DAC circuit 30 is replaced by the DAC circuit 100, andtherefore its explanation is omitted.

FIG. 1 shows a configuration of the DAC circuit 100 in accordance withthis first exemplary embodiment. Similarly to the DAC circuit 30 shownin FIG. 13, polarity switches SW51 and SW52 are connected to the inputside and output side, respectively, of the DAC circuit 100 in this firstexemplary embodiment. As shown in FIG. 1, the DAC circuit 100 includes aPchDAC 31, an NchDAC 32, a ladder resistor unit 33, and a voltage supplycontrol unit 110. Assume that the selection voltages selected for adigital gray-scale signal by the PchDAC 31 and the NchDAC 32 have asimilar relation to the graph shown in FIG. 14.

The voltage supply control unit 110 includes voltage supply controlcircuits 111 and 112. The voltage supply control circuit 111 receives avoltage supplied from an external terminal TVP1 and a power-supplyvoltage VDD2 supplied from a power-supply voltage terminal VDD2. Then,it outputs an output voltage Vout1 (which is explained later) to theladder resistor unit 33. The voltage supply control circuit 112 receivesa voltage supplied from an external terminal TVP64 and the power-supplyvoltage VDD2 supplied from the power-supply voltage terminal VDD2. Then,it outputs an output voltage Vout2 (which is explained later) to theladder resistor unit 33.

FIG. 2 shows a configuration of the voltage supply control circuit 111.As shown in FIG. 2, the voltage supply control circuit 111 includescomparison detectors CMP111 and CMP112, a control circuit CNT113, anoutput amplifier AMP114, a switch circuit SW115, an input terminalIN116, and an output terminal OUT117.

The input terminal IN116 receives a voltage supplied from the externalterminal TVP1. Note that the potential appearing at this input terminalIN116 is represented as “input voltage Vin1”.

The output amplifier AMP114 outputs a voltage corresponding to apotential level at a node B to the output terminal OUT117. The outputamplifier AMP114 is formed as a voltage follower circuit. Note that thepotential appearing at this output terminal OUT117 is represented as“output voltage Vout1”.

The comparison detector CMP111 monitors the power-supply voltage VDD2and the output voltage Vout1, and detects a potential difference betweenthem. Then, it outputs a detection result to the control circuit CNT113.

The comparison detector CMP112 monitors the input voltage Vin1 and theoutput voltage Vout1, and detects a potential difference between them.Then, it outputs a detection result to the control circuit CNT 113.

The switch circuit SW115 is connected between the node B and the inputterminal IN116. Then, the On/Off state of the switch circuit SW115 iscontrolled according to a switch control signal S2 output by the controlcircuit CNT113. For example, when a switch control signal S2 at a highlevel is input to the switch circuit SW115 it becomes an On-state andelectrically connects the node B to the input terminal IN116. Further,when a switch control signal S2 at a low level is input to the switchcircuit SW115, it becomes an Off-state and electrically cuts off thenode B from the input terminal IN116.

The control circuit CNT113 outputs a voltage control signal S1 to thenode B according to the detection results of the comparison detectorsCMP111 and CMP112, and also outputs a switch control signal S2 to theswitch circuit SW115. More specifically, the control circuit CNT113outputs a voltage control signal S1 having a potential levelsubstantially equal to the power-supply voltage VDD2 to the node Baccording to the detection result of the comparison detector CMP111 sothat the potential difference between the power-supply voltage VDD2 andthe output voltage Vout1 is kept from becoming wider. Further, based onthe detection result of the comparison detector CMP112, when thepotential difference between the input voltage Vin1, i.e., voltagesupplied from the external terminal TVP1 and the output voltage Vout1becomes a predetermined value (e.g., about 0.2V), the control circuitCNT113 performs control to raise the switch control signal S2 to a highlevel. Note that an assumption is made here that the output of thevoltage control signal S1 is stopped at the moment when the switchcontrol signal S2 rises to a high level.

FIG. 3 shows a timing chart for explaining an operation of the voltagesupply control circuit 111. As shown in FIG. 3, firstly, thepower-supply voltage VDD2 is turned on at a time t11 and the potentialof the power-supply voltage VDD2 gradually rises. At this point, thecontrol circuit CNT113 raises the potential level of the voltage controlsignal S1 according to the detection result of the comparison detectorCMP111 so that the potential difference between the power-supply voltageVDD2 and the output voltage Vout1 is kept from becoming wider. As aresult, the output amplifier AMP114 outputs a voltage substantiallyequal to the power-supply voltage VDD2 as the output voltage Vout1.

Meanwhile, the comparison detector CMP112 detects that no voltage issupplied from the external terminal TVP1 or that the potential of thesupplied voltage is low. The control circuit CNT 113 maintains theswitch control signal S2 at a low level based on this detection result,and the switch circuit SW115 electrically cuts off the node B from theinput terminal IN116.

Next, at a time t12, the voltage supplied from the external terminalTVP1 is turned on and the potential of the input voltage Vin1 graduallyrises. Further, at a time t13, the comparison detector CMP112 detectsthat the potential difference between the input voltage Vin1 and theoutput voltage Vout1 becomes a predetermined value. The control circuitCNT113 raises the switch control signal S2 to a high level based on thisdetection result, and the switch circuit SW115 electrically connects thenode 13 to the input terminal IN116. As a result, the potential of theinput voltage Vin1, i.e., the voltage supplied from the externalterminal TVP1 is input to the output amplifier AMP114. Therefore, theoutput amplifier AMP114 outputs a voltage substantially equal to thevoltage supplied from the external terminal TVP1 as the output voltageVout1.

Note that the configuration of the voltage supply control circuit 112 issimilar to that of the voltage supply control circuit 111. However, avoltage supplied from the external terminal TVP64 is input to the inputterminal IN116 of the voltage supply control circuit 112. In thefollowing explanation, the voltage supplied from the external terminalTVP64 is referred to as “input voltage Vin2” (Vin2<Vin1) as necessary.Further, an assumption is made that an output voltage Vout2(Vout2≦Vout1) is output to the output terminal OUT117 of the voltagesupply control circuit 112.

FIG. 4 shows a detailed configuration of a PchDAC 31 and a ladderresistor unit 33. Note that the configurations of the PchDAC 31 and theladder resistor unit 33 are similar to those described above withreference to FIG. 15, and therefore their explanations are omitted here.The configuration shown in FIG. 4 is different from that shown in FIG.15 in that the external terminals TVP1 and TVP64 connected to the ladderresistor unit 33 in FIG. 15 are replaced by the voltage supply controlcircuits 111 and 112 in FIG. 4. Because of this modification, theselection voltages VP2 to VP63 output from the ladder resistor unit 33to the PchDAC 31 are generated as intermediate potentials between theoutput voltages Vout1 and Vout2.

FIG. 5 is a schematic diagram showing a sequence of an LCD driver IC inaccordance with this first exemplary embodiment performed upon power-up.As shown in FIG. 5, firstly, the power-supply voltage VDD1 around 4Vthat is used by the logic circuit 10 rises at a time t1. Then, at a timet2, the logic circuit 10 starts to operate and thereby outputs an outputsignal SGNL. Next, at a time t11, the power-supply voltage VDD2 forhigh-voltage driver power supply rises. At this point, as explainedabove with reference to FIG. 4, the output voltage Vout1. Vout2 from thevoltage supply control circuit 111, 112 rises so as to follow the riseof the power-supply voltage VDD2. Then, at a time t12, the potential ofthe input voltage Vin1, Vin2, i.e., voltage supplied from the externalterminal TVP1, TVP64 rises. At a time t13, the potential differencebetween the input voltage Vin1, Vin2 and the output voltage Vout1, Vout2becomes a predetermined value, and therefore the switch circuit SW115becomes an On-state. As a result, the output voltages Vout1 and Vout2become voltages substantially equal to the voltages supplied from theexternal terminals TVP1 and TVP64 respectively. As a result, thepotentials of the selection voltages VP1 to VP64, which are suppliedfrom the ladder resistor unit 33 to the PchDAC 31, also rise so as tofollow the rise of the power-supply voltage VDD2.

In the DAC circuit 30 in related art shown in FIG. 13, even when thepower-supply voltage VDD2 has risen, the voltage VP1, VP64 from theexternal terminal has not risen sufficiently at this point. Therefore,as shown in FIG. 17, the potential difference VR from the power-supplyvoltage VDD2 could exceed the half of the power-supply voltage VDD2. Insuch a case, the potentials of the selection voltages VP1 to VP64, whichare supplied from the ladder resistor unit 33 to the PchDAC 31, alsoexceed the half of the power-supply voltage VDD2. Therefore, there is apossibility that they exceed the withstand voltage between the back-gateand the source, between the back-gate and the drain, and between theback-gate and the gate of the PMOS transistor constituting each switchcircuit of the PchDAC 31.

In contrast to this, in the DAC circuit 100 in accordance with thisfirst exemplary embodiment of the present invention, even when thevoltage VP1, VP64 from the external terminal has not risen sufficiently,the output voltage Vout1, Vout2 from the voltage supply control circuit111, 112 rises so as to follow the rise of the power-supply voltage VDD2as shown in FIGS. 3 and 5. As a result, the potentials of the selectionvoltages VP1 to VP64, which are supplied from the ladder resistor unit33 to the PchDAC 31, also rise so as to follow the rise of thepower-supply voltage VDD2. Therefore, it is possible to solve theproblem that occurs in the DAC circuit 30 in the related art, i.e., theproblem that the potential difference exceeds the withstand voltagebetween the back-gate and the source, between the back-gate and thedrain, and between the back-gate and the gate of the PMOS transistorconstituting each switch circuit of the PchDAC 31.

Further, since this problem is solved, there is no need to giveconsideration to the component-withstand margin of the PMOS transistorconstituting each switch circuit of the PchDAC 31, thus making itpossible to achieve the chip-shrinking corresponding to the withstandvoltage equivalent to the half of the power-supply voltage VDD2.Furthermore, since the voltages supplied from the external terminalsTVP1 and TVP64 can be turned on at an arbitrary timing, there is no needto add any additional control circuit that controls the power-upsequence in the power supply that generates the voltages VP1 and VP64supplied through the external terminals, thus eliminating the demeritsuch as increase in the design costs and increase in the circuit size.

Further, the only requirement for the voltage supply control circuits111 and 112 is to raise the output voltages Vout1 and Vout2 so as tofollow the rise of the power-supply voltage VDD2. Therefore, aconfiguration shown in FIG. 6, for example, may be also employed. Asshown in FIG. 6, the voltage supply control circuit 111 includescomparison detectors CMP111 and CMP112, a control circuit CNT113, switchcircuits SW115 and SW118, an input terminal IN116, and an outputterminal OUT117.

In the voltage supply control circuit 111 shown in FIG. 6, when thepower-supply voltage VDD2 rises, the switch circuit SW118 becomes anOn-state by a control signal S1 according to the detection result of thecomparison detector CMP111 so that the potential difference between thepower-supply voltage VDD2 and the output voltage Vout1 is kept frombecoming wider. Further, based on the detection result of the comparisondetector CMP112, when the potential difference between the input voltageVin1, i.e., voltage supplied from the external terminal TVP1 and theoutput voltage Vout1 becomes a predetermined value, the switch circuitSW115 becomes an On-state by a switch control signal 52. Note that theswitch circuit SW118 is turned off by the voltage control signal S1 atthe moment when the switch circuit SW115 is turned on by the switchcontrol signal 52. Note that the voltage supply control circuit 112 hasa similar configuration to that of the voltage supply control circuit111.

Second Exemplary Embodiment

A second specific exemplary embodiment to which the present invention isapplied is explained hereinafter in detail with reference to thedrawings. Similarly to the first exemplary embodiment, the presentinvention is applied to a DAC circuit 100 of an LCD driver IC of aliquid-crystal display device in this second exemplary embodiment. Thesecond exemplary embodiment is different from the first exemplaryembodiment in the configuration of the voltage supply control circuits111 and 112. Therefore, the second exemplary embodiment is explainedwith particular emphasis on that difference. The remaining commonconfiguration was already explained with the first exemplary embodiment,and therefore its explanation is omitted.

FIG. 7 shows a configuration of the voltage supply control circuit 111in accordance with second exemplary embodiment. As shown in FIG. 7, thevoltage supply control circuit 111 includes comparison detectors CMP111and CMP112, a control circuit CNT113, an output amplifier AMP114, aswitch circuit SW115, an input terminal IN116, and an output terminalOUT117. However, the second exemplary embodiment is different from thefirst exemplary embodiment in the following point.

The comparison detector CMP111 monitors a voltage equivalent to the halfof the power-supply voltage VDD2 (hereinafter referred to as “referencevoltage ½ VDD2”) and the output voltage Vout1, and detect a potentialdifference between them. Then, it outputs a detection result to thecontrol circuit CNT 113. Note that the reference voltage ½ VDD2 may begenerated by dividing the power-supply voltage VDD2 with twoseries-connected resistors. Further, the reference voltage is notlimited to the voltage equivalent to the half of the power-supplyvoltage VDD2. That is, the reference voltage may be any voltage equal toor higher than ½ VDD2.

The comparison detector CMP112 monitors the input voltage Vin1 and thereference voltage ½ VDD2, and detects a potential difference betweenthem. Then, it outputs a detection result to the control circuit CNT113.

The control circuit CNT113 outputs a voltage control signal S1 to thenode B according to the detection results of the comparison detectorsCMP111 and CMP112, and also outputs a switch control signal S2 to theswitch circuit SW115.

More specifically, the control circuit CNT113 outputs a voltage controlsignal S1 having a potential level substantially equal to the referencevoltage ½ VDD2 to the node B according to the detection result of thecomparison detector CMP111 so that the potential difference between thereference voltage ½ VDD2 and the output voltage Vout1 is kept frombecoming wider. Then, when the input voltage Vin1 becomes equal to orhigher than the reference voltage ½ VDD2 based on the comparison resultof the comparison detector CMP112, the control circuit CNT113 raises theswitch control signal S2 to a high level and thereby brings the switchcircuit SW115 into an On-state. Note that an assumption is made herethat the output of the voltage control signal S1 is stopped at themoment when the switch control signal S2 rises to a high level. Theother configuration is similar to that of the first exemplaryembodiment.

FIG. 8 shows a timing chart for explaining an operation of the voltagesupply control circuit 111. As shown in FIG. 8, firstly, thepower-supply voltage VDD2 is turned on at a time t21 and the potentialof the power-supply voltage VDD2 gradually rises. Further, the referencevoltage ½ VDD2, which is the half of the power-supply voltage VDD2,rises at the same time. At this point, the control circuit CNT113 raisesthe potential level of the voltage control signal S1 according to thedetection result of the comparison detector CMP111 so that the potentialdifference between the reference voltage ½ VDD2 and the output voltageVout1 is kept from becoming wider. As a result, the output amplifierAMP114 outputs a voltage substantially equal to the reference voltage ½VDD2 as the output voltage Vout1.

Meanwhile, the comparison detector CMP112 detects that no voltage issupplied from the external terminal TVP1 or that the potential of thesupplied voltage is low. The control circuit CNT113 maintains the switchcontrol signal S2 at a low level based on this detection result, and theswitch circuit SW115 electrically cuts off the node B from the inputterminal IN116.

Next, at a time t22, the voltage supplied from the external terminalTVP1 is turned on and the potential of the input voltage Vin1 graduallyrises. Further, at a time t13, the comparison detector CMP112 detectsthat the input voltage Vin1 becomes equal to or higher than thereference voltage ½ VDD2. The control circuit CNT113 raises the switchcontrol signal S2 to a high level based on this detection result, andthe switch circuit SW115 electrically connects the node B to the inputterminal IN116. As a result, the potential of the input voltage Vin1,i.e., voltage supplied from the external terminal TVP1 is input to theoutput amplifier AMP114. Therefore, the output amplifier AMP114 outputsa voltage substantially equal to the voltage supplied from the externalterminal TVP1 as the output voltage Vout1.

Note that the configuration of the voltage supply control circuit 112 issimilar to that of the voltage supply control circuit 111. However, avoltage supplied from the external terminal TVP64 is input to the inputterminal IN116 of the voltage supply control circuit 112.

FIG. 9 is a schematic diagram showing a sequence of an LCD driver IC inaccordance with this second exemplary embodiment performed uponpower-up. As shown in FIG. 9, firstly, the power-supply voltage VDD1around 4V that is used by the logic circuit 10 rises at a time t1. Then,at a time t2, the logic circuit 10 starts to operate and thereby outputsan output signal SGNL. Next, at a time t21, the power-supply voltageVDD2 for high-voltage driver power supply rises. At this point, asexplained above with reference to FIG. 8, the output voltage Vout1,Vout2 from the voltage supply control circuit 111, 112 follows the riseof the power-supply voltage VDD2 and the half voltage of thepower-supply voltage VDD2 is output.

Then, at a time t22, the potential of the input voltage Vin1, Vin2,i.e., voltage supplied from the external terminal TVP1, TVP64 rises. Ata time t23, the potential of the input voltage Vin1, Vin2 becomes equalto or higher than the half voltage of the power-supply voltage VDD2, andtherefore the switch circuit SW115 becomes an On-state. As a result, theoutput voltages Vout1 and Vout2 become voltages substantially equal tothe voltages supplied from the external terminals TVP1 and TVP64respectively. As a result, the potentials of the selection voltages VP1to VP64, which are supplied from the ladder resistor unit 33 to thePchDAC 31, also rise so as to follow the rise of the power-supplyvoltage VDD2.

As has been described above, in the DAC circuit 100 in accordance withthe second exemplary embodiment of the present invention, since thevoltage supply control circuits 111 and 112 have the configuration likethe one shown in FIG. 8, the half voltage of the power-supply voltageVDD2 is output so as to follow the rise of the power-supply voltage VDD2during the period in which the voltage VP1, VP64 from the externalterminal has not risen sufficiently. Then, when voltage VP1, VP64 fromthe external terminal becomes equal to or higher than the half voltageof the power-supply voltage VDD2, a potential substantially equal to thevoltage VP1, VP64 is output.

As a result, similarly to the first exemplary embodiment, even when thevoltage VP1, VP64 from the external terminal has not risen sufficiently,it is possible to prevent the potential difference from exceeding thewithstand voltage between the back-gate and the source, between theback-gate and the drain, and between the back-gate and the gate of thePMOS transistor constituting each switch circuit of the PchDAC 31.

Further, the only requirement for the voltage supply control circuits111 and 112 is to adjust the output voltages Vout1 and Vout2 to the halfvoltage of the power-supply voltage VDD2 so as to follow the rise of thepower-supply voltage VDD2. Therefore, a configuration shown in FIG. 10,for example, may be also employed. As shown in FIG. 10, the voltagesupply control circuit 111 includes a comparison detector CMP112, acontrol circuit CNT113, switch circuits SW115 and SW118, an inputterminal 1N116, and an output terminal OUT117.

In the voltage supply control circuit 111 shown in FIG. 10, when thepower-supply voltage VDD2 rises and hence the reference voltage ½ VDD2rises, the comparison detector CMP112 monitoring the output voltageVout1 performs a comparison to determine whether the output voltageVout1 is equal to or higher than the reference voltage ½ VDD2 or not andoutputs the determination result to the control circuit CNT113. When theoutput voltage Vout1 is equal to or lower than the reference voltage ½VDD2, the control circuit CNT113 brings the switch circuit SW118 into anOn-state and brings the switch circuit SW115 into an Off-state. Then,based on the detection result of the comparison detector CMP112, whenthe input voltage Vin1, i.e., voltage supplied from the externalterminal TVP1 becomes equal to or higher than the reference voltage ½VDD2, the control circuit CNT113 brings the switch circuit SW118 into anOff-state and brings the switch circuit SW115 into an On-state.

Even with the configuration like this, the voltage supply controlcircuit 111 outputs the half voltage of the power-supply voltage VDD2 soas to follow the rise of the power-supply voltage VDD2 during the periodin which the voltage VP1, VP64 from the external terminal has not risensufficiently. Then, when the voltage VP1, VP64 from the externalterminal becomes equal to or higher than the half voltage of thepower-supply voltage VDD2, the voltage supply control circuit 111outputs a potential substantially equal to the voltage VP1, VP64.

Note that the present invention is not limited to the above-describedexemplary embodiments, and various modifications can be made withoutdeparting from the spirit and scope of the present invention. Forexample, a voltage supply control unit 210 may be connected between theladder resistor unit 33 and the PchDAC 31 as shown in FIG. 11. Thevoltage supply control unit 210 includes the same number of voltagesupply control circuits as the number of voltages VP1 to VP64 suppliedby the PchDAC 31, and each of the voltage supply control circuits has asimilar configuration as that of the voltage supply control circuit 111.Even with the configuration like this, it is possible to solve theproblem that the potential difference exceeds the withstand voltagebetween the back-gate and the source, between the back-gate and thedrain, and between the back-gate and the gate of the PMOS transistorconstituting each switch circuit of the PchDAC 31, though the circuitsize may increase.

Further, although the selection voltages are generated by dividingvoltages supplied from the two external terminals TVP1 and TVP64 withthe ladder resistor unit 33 in the first and second exemplaryembodiments, the number of the external terminals is not limited to two.That is, the selection voltages may be generated by using voltagessupplied from three or more external terminals.

While the invention has been described in terms of several exemplaryembodiments, those skilled in the art will recognize that the inventioncan be practiced with various modifications within the spirit and scopeof the appended claims and the invention is not limited to the examplesdescribed above.

Further, the scope of the claims is not limited by the exemplaryembodiments described above.

Furthermore, it is noted that, Applicant's intent is to encompassequivalents of all claim elements, even if amended later duringprosecution.

The first and second exemplary embodiments can be combined as desirableby one of ordinary skill in the art.

1. A D/A converter circuit for a drive circuit provided in a displaydevice, comprising: a D/A converter unit that selects one of a pluralityof selection voltages according to an input digital gray-scale signal,and outputs the selected selection voltage as an analog gray-scalesignal; a first power-supply voltage terminal through which a firstpower-supply voltage is supplied to a first terminal of a transistorconstituting the D/A converter unit upon power-up of the D/A converterunit; and a voltage supply control unit that detects a potentialdifference between the first power-supply voltage and a second voltageused to generate the selection voltages, outputs a voltage correspondingto the first power-supply voltage to a second terminal of the transistorconstituting the D/A converter unit when the potential difference islarger than a predetermined value, and outputs a voltage correspondingto the second voltage to the second terminal of the transistorconstituting the D/A converter unit when the potential difference issmaller than the predetermined value.
 2. The D/A converter according toclaim 1, wherein the voltage supply control unit comprises a switchcircuit, when the potential difference is larger than the predeterminedvalue, the voltage supply control unit brings the switch circuit into acut-off state and outputs a voltage corresponding to the firstpower-supply voltage, and when the potential difference is smaller thanthe predetermined value, the voltage supply control unit brings theswitch circuit into a conductive state and outputs a voltagecorresponding to the second voltage.
 3. The D/A converter according toclaim 2, wherein the voltage supply control unit comprises a controlcircuit and an amplifier that outputs a voltage according to an inputvoltage, the switch circuit is connected between an input of theamplifier and a terminal through which the second voltage is supplied,and the control circuit brings the switch circuit into a cut-off statewhen the potential difference is larger than the predetermined value,and brings the switch circuit into a conductive state when the potentialdifference is smaller than the predetermined value.
 4. The D/A converteraccording to claim 1, further comprising a ladder resistor unit thatgenerates the plurality of selection voltages corresponding to thesecond voltage.
 5. The D/A converter according to claim 1, wherein thepredetermined value is a value smaller than a half of the firstpower-supply voltage.
 6. The D/A converter according to claim 1, whereinthe transistor constituting the D/A converter unit is a PMOS transistor.7. The D/A converter according to claim 6, wherein the first terminal ofthe transistor is a back-gate voltage supply terminal.
 8. The D/Aconverter according to claim 6, wherein the second terminal of thetransistor is either a drain terminal or a source terminal.
 9. The D/Aconverter according to claim 1, wherein the second voltage is suppliedfrom an external terminal of the D/A converter circuit.
 10. The D/Aconverter according to claim 1, wherein the display device is aliquid-crystal display device, and the drive circuit is a source driverfor dot inversion drive.
 11. A voltage supply control method for a D/Aconverter circuit of a drive circuit provided in a display device,supplying a voltage corresponding to a first power-supply voltage to afirst terminal of a transistor constituting a D/A converter unit whenthe D/A converter unit is powered on, the D/A converter unit beingconfigured to select one of a plurality of selection voltages accordingto an input digital gray-scale signal and output the selected selectionvoltage as an analog gray-scale signal; and when a potential differencebetween the first power-supply voltage and a second voltage used togenerate the selection voltages is larger than a predetermined value,the first power-supply voltage is output to a second terminal of thetransistor constituting the D/A converter unit, whereas when thepotential difference is smaller than the predetermined value, a voltagecorresponding to the second voltage is output to a second terminal ofthe transistor constituting the D/A converter unit.
 12. The voltagesupply control method for a D/A converter circuit according to claim 11,wherein the predetermined value is a value smaller than a half of thefirst power-supply voltage.
 13. The voltage supply control method for aD/A converter circuit according to claim 11, wherein the transistor is aPMOS transistor and the first terminal is a back-gate voltage supplyterminal, and the second terminal of the transistor is either a drainterminal or a source terminal.